As system complexity and operational speeds increase, the power consumption of integrated circuits increases dramatically. Additionally, the IC supply voltage continues to drop with the inevitable scaling of VLSI technology.
Reducing the nominal supply voltage is accompanied by a reduction in device noise margins, making components more vulnerable to power supply noise. This noise consists of the dynamic AC voltage fluctuation due to the frequency dependent distributed parasitics inherent in today's power distribution systems, and the DC voltage drop (i.e., “IR” drop).
In a microelectronic system, the system's IR drop may be budgeted into three portions: on-chip, package and board. On-chip IR drop has been extensively studied because the resistive loss is severe due to the fine feature-size of the on-die power grid.
To reduce the IR drop and improve power integrity, decoupling capacitors are typically mounted on a top surface of a packaging substrate or disposed within the packaging substrate. However, the aforesaid substrate-level decoupling capacitors are still not close enough to the IC die in the package to cope with the on-chip IR drop.
It is desirable to place a high-performance capacitor as close to the IC die as possible to shorten the transient response time.